Without limiting the scope of the invention, its background is described in conjunction with automotive electrical systems, as an example.
Heretofore, in this field, high-power electronic components had to be fabricated on integrated circuit chips separate from IC chips for low-power, logic components. Conventionally, high-power transistors had different processing requirements that were not easily integrable with low-power logic devices, such as 5-volt insulated-gate field transistors. On the one hand, certain voltage regulator and power devices mandate that power transistors directly exposed to the usual 12-volt conventional automobile electrical system be capable of withstanding transients that may be as high as 60 volts. On the other hand, the implantation, isolation and doping characteristics of these devices made their cofabrication with smaller, process-labile devices difficult. It is, however, desirable for automobile system microcontrollers to be monolithis, i.e., fabricated on the surface of one semiconductor chip, rather than have one chip for voltage regulation and other high-power applications and another chip for the performance of logic and the like.
Another problem which has arisen in semiconductor chip fabrication concerns electrically-erasable, electrically-programmable read-only memory (EEPROM) cells that are fabricated using a so-called "stack" process. According to this process, a first level of polysilicon conductor is deposited and doped to form the floating gate of the EEPROM cell, but is only partially defined in a first etch. After the formation of an insulator on the first level poly, such as an oxide/nitride/oxide sandwich, a second level poly layer is deposited on the cell. The first and second level poly layers are then etched back in a single "stack" that makes the lateral margins of the control gate and the floating gate of the EEPROM cell congruent.
A problem occurs in this type of cell when the poly 2 layer is also used to form the control gate the row select gating transistor. In this instance, the cell is often prone to an overetch of the poly, creating trenches on either side of the row select transistor gate that ruin the cell. Further, so called "stack" double level poly EEPROM cells are more prone to breakdown on their relatively exposed floating gate lateral margins due to high electrical fields. Because of the relatively low reliability of these "stack" cells, memories that are incorporated, for example, in highly noisy or stressful environments such as automotive systems are arranged in transistors everywhere, since first-level poly is needed triple- or other multi-bit voting memories rather than in single-bit memories.
K. Y. Chang et al has built a non-stack cell, as described in "Advanced High Voltage CMOS Process for Custom Logic Circuits with Embedded EEPROM," IEEE 1988 Custom I. C. Conf., 25.5.1. However, this cell is not bit-addressable and has the second level poly deposited after the source/drain implantation. Such a cell, as used on an integrated circuit chip having other devices, would force the manufacturer to use high-voltage transistors everywhere, since first-level poly is needed for the row transistor. A typical "stack" cell process is shown by Dumitru Cioaca et aI, in "A Million-Cycle CMOS 256K EEPROM," IEEE J of Solid State Circuits, V 22, N 5, p 684, 1987. This cell has achieved high reliability by using redundancy (the Q cell has two bits per cell) and oxynitride for the tunnel diode. The cell uses a stack pattern for high density, but is not bit addressable.
It is therefore desirable to build a high-reliability, bit-addressable cell fabricated by a non-stack process which will allow single-bit memories, and it is desirable to design an integrated fabrication process that creates both low- and high-voltage semiconductor devices on a single chip.